Switched capacitor programmable gain and attenuation amplifier circuit

ABSTRACT

A digitally programmable switched capacitor gain and attenuation circuit that uses the same switched capacitor array for a multitude of different gain and/or attenuation settings with a single operational amplifier is disclosed. With the top plates of the capacitors connected to the operational amplifier input, the unique switching of the bottom plates of the capacitor array elements between three voltages—the circuit output, the circuit input, or a chosen reference voltage such as a power supply midpoint voltage or a ground voltage of the circuit, makes this circuit arrangement&#39;s component area smaller and the operational amplifier&#39;s design specification less demanding for applications such as a digital camera front end analog processor.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to electronic circuits and, more particularly, to an amplifier circuit providing programmable gain and attenuation.

BACKGROUND OF THE INVENTION Description of the Prior Art

Switched capacitor circuit stages using multi-phase docks are found in a number of sampled analog data applications such as filters and signal conversion circuits, including analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). They are additionally used in emerging technologies such as image processing in digital cameras, digital camcorders, and digital high definition televisions.

An early switched capacitor implementation of the present day fast interstage amplifier with a fixed gain of two used in pipelined ADCs is disclosed in “High-Resolution Pipelined Analog-to-Digital Conversion,” by Sehat Sutarja, University of California, Berkeley, 1988, pp. 40-43, which shows a 25 percent increase in speed. The switched capacitor configuration of this reference also has the unique property that the noise gain equals the signal gain, which is different from many versions of switched capacitor gain/integrator stages where the noise gain equals the signal gain plus one. See, for example, U.S. Pat. Nos. 4,354,250, 4,404,525, 4,453,258, 4,555,668 and 5,574,457.

If one uses a switched capacitor gain stage according to the Sutarja reference for a finite signal bandwidth application, one does not need an amplifier with such a large amplifier bandwidth as compared to other switched capacitor gain stages mentioned above where one needs an amplifier with a larger bandwidth thereby expending more power for the same result. The Sutarja gain stage has one capacitor that switches the bottom plate of the capacitor from the input signal to the output of the amplifier and has another capacitor that switches the bottom plate of the capacitor from the input signal to ground. Both capacitor top plates are connected to the amplifier input and a clocked grounding switch. The first capacitor's bottom plate is never switched to ground and the second capacitor is never switched to the output. The Sutarja switched capacitor gain stage has both the capacitors equal to each other and does not do any signal attenuation only signal gain.

Attenuation circuits mainly comprise of resistors with field effect transistors used as either switches or active resistive elements such as taught in U.S. Pat. No. 5,157,323. A known switched capacitor adjustable attenuator circuit, such as shown in U.S. Pat. No. 4,468,749, uses a predetermined time to discharge a capacitor to ground in order to provide attenuation. The configuration uses a feedback capacitor that is switched from across the op amp input and output on one clock cycle to both ends grounded on the other cycle.

For a programmable gain and attenuation circuit, it would be advantageous for a single switched capacitor circuit to provide both gain and attenuation in the same embodiment, and without using FETs and resistors for attenuation. Furthermore, it would be desirable to minimize the power expended by an operational amplifier in such an arrangement for gain settings.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a programmable gain and attenuation circuit in which both gain and attenuation are provided by the same capacitor array.

It is also an object of the present invention to provide a programmable gain and attenuation circuit which does not require the use of FETs and resistors for attenuation.

It is further an object of the present invention to provide a programmable gain and attenuation circuit which minimizes the power expended by the operational amplifier for gain settings.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features of the present invention may be more fully understood from the detailed description, read in conjunction with the accompanying drawings, wherein:

FIGS. 1a, 1 b and 1 c illustrate gain stage switching in accordance with the prior art;

FIGS. 2a and 2 b illustrate a novel switching arrangement of the capacitors of FIG. 1a to provide attenuation in accordance with the present invention;

FIG. 3 illustrates a portion of an array of capacitors in a single-ended configuration in accordance with the present invention; and

FIG. 4 illustrates a portion of arrays of capacitors in a double-ended configuration in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1a illustrates a gain stage in accordance with the prior art. This gain stage switches both the input and feedback capacitors on different clock phases to provide gain. On clock phase_(φ1), when switches S_(1a), S_(1b) and S_(1c) are closed and switch S₂ is open, the bottom plates of input capacitance C_(s) and feedback capacitance C_(F) are charged to voltage V_(in), as shown in FIG 1 b. On clock phase _(φ2), when switches S_(1a), S_(1b) and S_(1c) are open and switch S₂ is closed, the bottom plate of C_(F) is switched from the input to the output around the amplifier and is charged to voltage V_(out), while the bottom plate of C_(S) is switched to ground, as shown in FIG. 1c. The gain is expressed as

GAIN=V _(out) /V _(in)=(C _(S) +C _(F))/C _(F).

Since C_(S) is always greater than zero, the circuit of FIG. 1a always provides gain.

In accordance with the present invention, attenuation can be provided by first charging the C_(S) and C_(F) capacitors, then, in addition to all of the C_(S) and C_(F) capacitors, additional capacitors are switched in to give C_(F) capacitance on phase _(φ2) around the amplifier.

FIGS. 2a and 2 b illustrate an example demonstrating the operation of the present invention. Referring to FIG. 2a, 160-C_(UNIT) capacitors are charged during phase_(φ1) to voltage V_(in), while 64-C_(UNIT) capacitors are idle with ground on both ends, with zero charge across the capacitors. On phase _(φ2), both the 160-C_(UNIT) capacitors and the 64-C_(UNIT) capacitors are switched around the amplifier, with no capacitors switched to ground, as in the gain case. This gives a gain of

GAIN=(C _(s) +C _(F))/C _(F)=(224−64)/224=160/224=0.714,

which is less than one, thereby providing attenuation, Thus, using the same array capacitors, attenuation can be provided by a gain stage simply by switching the capacitors differently. This may be extended to any arbitrary sized array to give both attenuation and gain if the unit values are chosen so that the composition of all the attenuation units are switched around the operational amplifier and the sum of the capacitors gives the correct final value for the desired attenuation. In order to have linear gain in dB in any N×N array, the capacitor array is configured as in. FIG. 3. The array capacitor has either V_(in), V_(out) or V_(ground) connected, based on the proper decoding for gain or attenuation.

With the top plates of the capacitors connected to the operational amplifier input, the unique switching of the bottom plates of the capacitor array elements between three voltages—the circuit output, the circuit input, or a chosen reference voltage such as a power supply midpoint voltage or a ground voltage of the circuit, makes this circuit arrangement's component area smaller and the operational amplifier's design specification less demanding for applications such as a digital camera front end analog processor.

FIG. 3 illustrates a portion of an array of capacitors in a single-ended configuration in accordance with the present invention; and

FIG. 4 illustrates a portion of arrays of capacitors in a double-ended configuration in accordance with the present invention.

While the principles of the present invention have been demonstrated with particular regard to the structures and methods disclosed herein, it will be recognized that various departures may be undertaken in the practice of the invention. The scope of the invention is not intended to be limited to the particular structures and methods disclosed herein, but should instead be gauged by the breadth of the claims which follow. 

What is claimed is:
 1. A programmable switched capacitor gain and attenuation circuit comprising: an operational amplifier; N capacitors, each of the N capacitors having a top plate coupled to a first input of the operational amplifier, wherein N is an integer greater than one; N switching networks, each of the N switching networks is coupled to a corresponding bottom plate of a corresponding one of the N capacitors, each of the N switching networks is operable to switch the corresponding bottom plate to any one of a first input node, a first output of the operational amplifier, and a common node; and M capacitors each having a top plate coupled to a second input of the operational amplifier, wherein M is equal to N.
 2. The circuit of claim 1 further comprising a switch coupled between the first input of the operational amplifier and the common node.
 3. The circuit of claim 2 further comprising a second input of the operational amplifier coupled to the common node.
 4. The circuit of claim 1 further comprising a second input of the operational amplifier coupled to the common node.
 5. The circuit of claim 4 wherein the first input of the operational amplifier is a negative input and the second input of the operational amplifier is a positive input.
 6. The circuit of claim 1 further comprising M switching networks, each of the M switching networks is coupled to a corresponding bottom plate of a corresponding one of the M capacitors, each of the M switching networks is operable to switch the corresponding bottom plate to any one of a second input node, a second output of the operational amplifier, and the common node.
 7. The circuit of claim 6 further comprising a switch coupled between the common node and the first and second input of the operational amplifier.
 8. The circuit of claim 6 wherein the first input of the operational amplifier is a negative input, the second input of the operational amplifier is a positive input, the first output of the operational amplifier is a negative output, and the second output of the operational amplifier is a positive output.
 9. The circuit of claim 1 further comprising a switch coupled between the common node and the first and second input of the operational amplifier. 